1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly relates to a semiconductor device including a silicon MOSFET (Metal Oxide Semiconductor Field Effect Transistor) for a high frequency, which has high resistance against occurrence of surges such as a discharge phenomenon, as well as a method of manufacturing the same.
2. Description of the Background Art
As a result of widespread use of cellular phones and practical use of wireless LAN (Local Area Network) in recent years, attention has been focused on high-frequency semiconductor devices, which are essential for achieving high performance, small sizes and low costs of such electronic devices. In many cases, materials of these high-frequency semiconductor devices are III-V semiconductors such as GaAs having a high electron mobility. In recent years, however, the sizes of silicon MOS transistors have been remarkably reduced to allow production of MOS transistors having gate lengths shorter than 0.2 xcexcm. The silicon MOS transistor having such a minute gate length can be applied to a high-frequency device in a gigahertz band because a trans-conductance Gm is remarkably improved and high-frequency characteristics are improved. However, the silicon MOS transistor having a gate length, which is reduced for use in a high-frequency device, has a lower resistance against a surge than conventional elements employing GaAs or the like. Therefore, it is necessary to take countermeasures against occurrence of surges such as electrostatic discharge.
Then, the countermeasures against disturbances such as electrostatic discharge will be described. When an electrostatically charged object comes into contact with another object, a discharge phenomenon may occur between these objects. This discharge phenomenon is called xe2x80x9cESD (ElectroStatic Discharge)xe2x80x9d. When ESD occurs in a semiconductor element, it may damage the semiconductor element. As typical models of the ESD, there are three models, i.e., (a) HBM (Human Body Model) which is a model of discharge from a charged human body to a semiconductor element, (b) MM (Machine Model) which is a model of discharge from a charged device to a semiconductor element and (c) CDM (Charge Device Model) which is a model of a phenomenon of discharge of electric charges carried on a semiconductor element itself to a grounded object. Among them, examples of current waveforms in (a) HBM and (c) CDM are shown in FIG. 59. It can be seen from FIG. 59 that a current stress of about 1 A occurs for a relatively long time of 100 ns in HBM, but a high current stress of about 10 A occurs for a very short time of 1 ns in CMD. In either of these models, a high current flows for a short time.
As described above, when ESD occurs, a high current is applied to the semiconductor element for a short time so that thermal destruction, i.e., melting by Joule heat, occurs. Further, insulation breakdown has occurred in some cases employing MOS transistor structures, which have been in the mainstream of LSI (Large-Scale Integration) silicon devices in recent years, because a high electric field due to ESD is applied to a gate oxide film of the MOS transistor. This insulation breakdown of the gate oxide film caused by ESD causes a significant obstacle to utilization of an inexpensive silicon semiconductor member. Countermeasures have been employed for avoiding the insulation breakdown of the gate oxide film. According to the countermeasures, an appropriate kind of protection circuit is formed between an I/O pin and an internal circuit so that a high-voltage surge caused upon occurrence of ESD may not reach the internal circuit. This protection circuit is called an ESD protection circuit. An object or target on a silicon wafer, which is connected to the foregoing I/O pin by wire bonding, is a pad. In the following description, therefore, a term xe2x80x9cI/O padxe2x80x9d is used instead of xe2x80x9cI/O pinxe2x80x9d.
In many cases, the ESD protection circuit is formed of a circuit, in which an MOS transistor in the off state is connected to an I/O signal line (M. -D. Ker et al., IEDM, pp. 889-892, 1996). FIG. 60 is a circuit diagram showing a semiconductor device, in which an MOS transistor in the off state is used as the ESD protection circuit. In FIG. 60, an n-channel MOS transistor 117n (which may be referred to as an xe2x80x9cnMOSxe2x80x9d hereinafter) and a p-channel MOS transistor 117p (which may be referred to as a xe2x80x9cpMOSxe2x80x9d hereinafter) are off. The nMOS has a drain D connected to an I/O signal line, and also have a gate G, a source S and a p-conductive well (which will be referred to as a xe2x80x9cp-wellxe2x80x9d hereinafter) W, which are all grounded. The pMOS has a drain D connected to the I/O signal line, and also have a gate, a source and an n-well all connected to an external supply voltage, which will be referred to as xe2x80x9cVddxe2x80x9d hereinafter. Since two MOS transistors 117p and 117n are off, these transistors do not pass any current during an ordinary operation, and do not affect ordinary device operations.
When a high-voltage surge due to ESD is applied through the I/O pad, parasitic bipolar transistor effects occur in the pMOS and nMOS as described below so that a path for a high current flow from the drain to the source is formed. FIG. 61 shows the parasitic-bipolar transistor effect of the MOS transistor. In the following description, it is assumed that a surge of a positive voltage is applied to the drain of the nMOS. First, the positive voltage surge is applied to an n+-type diffusion layer of drain D formed at a silicon substrate 101. When the voltage thus applied increases, breakdown occurs on a pn junction of the n+-type diffusion layer, which is reversely biased, so that large amounts of electrons and holes are produced by impact ionization. These electrons flow to drain D bearing a positive voltage, and these holes flow to grounded p-well W.
It is assumed that the flow of holes to the p-well causes a current of a magnitude of Ihole, and the p-well has a resistance value of Rsub. A voltage drop of Iholexc2x7Rsub occurs in the direction of depth of the p-well. This voltage drop causes a potential difference in the p-well so that the potential in the p-well region located at a shallow position immediately under the nMOS gate rises to a positive potential. In this operation, the n+-type diffusion layer of the drain, the shallow p-well region immediately under the gate and the n+-type diffusion layer of the source form an npn parasitic bipolar transistor. In this npn parasitic bipolar transistor, a reverse bias voltage is applied to a junction between the n+-type diffusion layer of the drain and the shallow p-well region under the gate, and a positive bias voltage is applied to a junction between the shallow p-well region under the gate and the n+-type diffusion layer of the source. By these voltages, the parasitic npn bipolar transistor is turned on.
In summary, when ESD occurs and a positive voltage is applied to the drain of the nMOS, which has a grounded gate and is off, the npn parasitic bipolar transistor is turned so that a large current can flow.
When a surge of a negative voltage is applied to the drain of the pMOS, effects similar to the above occur. Further, when a positive voltage is applied to the drain of the pMOS, the junction between the drain and n-well of the pMOS is subjected to a forward bias, and a current flows to the n-well. The on-operation in this case is usually expected in the pMOS. When a surge of a negative voltage is applied to a drain of the nMOS, a forward bias state is likewise attained and a current flows to the p-well similarly to the pMOS. The on-operation thus performed is also expected usually in the nMOS.
As described above, the ESD protection circuit using the MOS transistors in the off state can relieve a large current to the GND (ground) or Vdd when ESD occurs. As a result, it is possible to prevent flow of a large current in an internal circuit so that thermal destruction as well as insulation breakdown of the gate oxide film can be prevented.
For achieving the ESD protection function described above by the MOS transistor in the off state, it is necessary to keep a sufficiently large distance d between the gate electrode of each MOS transistor and the contact between the source and drain diffusion layers (FIG. 62). Distance d from the gate electrode to the contact between the source and drain diffusion layers must be in a range, e.g., from 5 xcexcm to 6 xcexcm according to the disclosure (M. -D. Ker et al., IEDM, pp. 889-892, 1996). It is stated that the purpose of increasing distance d is to increase the resistance and thereby avoid such a situation that the surge directly enters the gate to apply a stress to the gate.
Assuming that the contact has a diameter of c, the source/drain diffusion layer located between the gate electrodes has a width of 2d+c, as shown in FIG. 62. Therefore, the MOS transistor used for the ESD protection, which requires large distance d described above, has the source/drain diffusion layer of a large width. For example, according to the design rule of 0.2 xcexcm, c is generally equal to 0.2 xcexcm, and therefore the width (2d+c) of the source/drain diffusion layer takes a large value from 10.2 xcexcm to 12.2 xcexcm. Accordingly, the MOS transistor must have a gate width of 100 xcexcm or more for achieving the sufficient ESD protection function. According to the 0.2 xcexcm design rule, the parasitic capacitance of the source/drain diffusion layer per unit area, i.e., the depletion layer capacitance of the pn junction between the source/drain diffusion layer and the well, is equal to 1 fF/xcexcm2. Accordingly, it can be understood that the parasitic capacitance, which is formed between the source/drain diffusion layer of the MOS transistor used as the ESD protection element and the silicon substrate (well), takes the very large value from 1.02 pF to 1.22 pF.
As described above, the very large parasitic capacitance of the ESD protection element does not cause a problem in the semiconductor memory and logic device. However, the large parasitic capacitance causes a large problem in the high-frequency device employing the silicon MOS transistor. An impedance Z of a capacitance C has a magnitude of |Z| expressed by (1/(2xcfx80xc2x7fxc2x7C)). Therefore, the magnitude |Z| of the impedance of the capacitance C decreases as the frequency f increases for achieving a higher frequency. If capacitance C increases, the magnitude |Z| of impedance of capacitance C further decreases. More specifically, if a large capacitance of the source/drain diffusion layer is connected to a high-frequency signal line, the impedance of the source/drain layer has an extremely small magnitude with respect to a high frequency. Further, a semi-insulating silicon substrate of high resistance, which has a high quality similar to that of a GaAs substrate, is not available, and therefore it is obliged to use a low-resistance substrate as the silicon substrate.
FIG. 63 shows a schematic equivalent circuit of the ESD protection circuit employing the MOS transistors formed on the above silicon substrate. Referring to FIG. 63, since the silicon substrate connected to the capacitance has a small resistance, a majority of the high-frequency signal flowing through the high-frequency signal line flows to the MOS transistors provided for the ESD protection. Accordingly, a majority of the high-frequency signal is lost due to the resistance of the silicon substrate:
As described above, if the silicon MOS transistors are used for forming the ESD protection element, it is very difficult to implement the high-frequency semiconductor device having high reliability with respect to the high-frequency signal. However, the protection against the ESD is necessary. Therefore, several kinds of countermeasures have been employed or proposed. These will now be described.
For protecting the internal circuit from the ESD surge applied to the I/O pad of the high-frequency signal, the protection must be effected, depending on the portion of the grounded surface, for such four cases that:
(A) an ESD surge of a positive voltage flows into the I/O pad for the high-frequency signal, and the grounded surface is a GND pin;
(B) an ESD surge of a positive voltage flows into the I/O pad for the high-frequency signal, and the grounded surface is a Vdd pin;
(C) an ESD surge of a negative voltage flows into the I/O pad for the high-frequency signal, and the grounded surface is a GND pin; and
(D) an ESD surge of a negative voltage flows into the I/O pad for the high-frequency signal, and the grounded surface is a Vdd pin.
In the conventional ESD protection circuit described above, the surge flows to the grounded surface owing to the following operations, which correspond to the cases (A)-(D), respectively, so that the internal circuit is protected.
(A) The surge flows to the grounded surface (GND pin) owing to a parasitic bipolar effect induced by breakdown of the diffusion layer of the nMOS.
(B) The surge flows to the grounded surface (Vdd pin) owing to a diode forward operation of the diffusion layer of the pMOS.
(C) The surge flows to the grounded surface (GND pin) owing to a diode forward operation of the diffusion layer of the nMOS.
(D) The surge flows to the grounded surface (Vdd pin) owing to a parasitic bipolar effect induced by breakdown of the diffusion layer of the pMOS.
From the protection effects in the respective cases described above, it can be understood that the internal circuit is protected by utilizing both the breakdown, which is caused by the reverse voltage application, at the junction between the diffusion layer and the well of the MOS transistor as well as the forward operation.
However, it has been pointed out by M. -D. Ker et al., (IEEE J. Solid-State Circuits, vol. 35, No. 8, pp. 1194-1199, 2000) that the capability of ESD protection, which is performed when the operation causing the reverse breakdown at the junction of the diffusion layer, is significantly lower than the ESD protection capability in the forward operation.
Therefore, the manner of forming the following protection circuit for preventing an influence on characteristics of the high-frequency signal I/O pad has been known. Such a circuit is employed that pMOS and nMOS transistors 118p and 118n each having a large gate width are arranged between the Vdd and GND lines (FIG. 64). These gate widths are larger than those of the pMOS and nMOS transistors 117n and 117p connected to the high-frequency signal I/O pad. In this protection circuit, the following operations are performed for the respective cases described above.
(A) The surge is first passed to the Vdd line primarily by the diode forward operation of the diffusion layer of pMOS 117p. Then, the surge flows into pMOS 118p having the high gate width and the high ESD protection capability. In this pMOS 118p, the surge causes the breakdown of the diffusion layer, and the parasitic bipolar effect occurs so that pMOS 118p is turned on to form the flow path of the surge. Thereafter, the surge flows into nMOS 118n connected to pMOS 118p to cause the forward operation in nMOS 118n, and flows to the grounded surface (GND pin).
(B) The diode forward operation of the diffusion layer of pMOS 117p passes the surge to the grounded surface (Vdd pin).
(C) The diode forward operation of the diffusion layer of nMOS 117n passes the surge to the grounded surface (GND pin).
(D) The surge is first passed to the GND line primarily by the diode forward operation of the diffusion layer of nMOS 117n. Then, the surge flows into nMOS 118n having the high gate width and the high ESD protection capability. In this nMOS 118n, the surge causes the breakdown of the diffusion layer, and the parasitic bipolar effect occurs so that nMOS 118n is turned on to form the flow path of the surge. Thereafter, the surge flows into pMOS 118p connected to nMOS 118n to cause the forward operation in pMOS 118p, and flows to the grounded surface Vdd pin.
In the case of utilizing the ESD protection functions of MOS transistors 118p and 118n arranged between the Vdd and GND lines as described above, the breakdown operation may occur in these MOS transistors due to the reverse voltage application. Therefore, it is impossible to expect the good ESD protection characteristics in all the foregoing cases.
For overcoming the above problems, a manner of arranging a transient response clamp circuit 128 is arranged between the Vdd and GND lines as shown in FIG. 65 (M.-D. Ker et al., IEEE, J. Solid-State Circuits, vol. 35, No. 8, pp. 1194-1199, 2000). According to this circuit, the outflow of surge is achieved only by the diode forward operation in all the cases. Therefore, the ESD protection capability is improved, and it is possible to reduce significantly the gate width of MOS transistor in the ESD protection circuit connected to the high-frequency signal I/O pad. The arrangement of transient response clamp circuit 128 reduces a parasitic capacity added to the high-frequency signal I/O pad, and it is possible to avoid remarkable deterioration of the high-frequency characteristics, which may occur due to employment of the conventional ESD protection circuit.
The nMOSs forming the transient response clamp circuit described above is immediately turned on only in response to the ESD surge of a waveform having steep rising portions owing to an RC circuit structure. As a result, the ESD surge can flow from the Vdd line to the GND line, and vice versa. The transient response clamp circuit described above can clamp the voltages on the Vdd and GND lines with a low voltage, which does not cause the reverse breakdown of the MOS transistors connected to the high-frequency signal I/O pad. As a result, the ESD protection operation is achieved only by the diode forward operation in all the foregoing cases while keeping the small gate width and good high-frequency characteristics.
When the ESD surge does not flow, and a normal operation is performed, i.e., in the case where the Vdd voltage in a normal range is applied to the Vdd power supply pin, the waveform of Vdd voltage has slow rising portions so that the transient response clamp circuit 128 is not turned on. In the normal operation, therefore, a path between the Vdd and GND lines is cut off so that the transient response clamp circuit exerts no influence on the normal operation. As described above, the ESD protection circuit with the transient response clamp circuit, which can reduce the parasitic capacitance, is very useful as the ESD protection circuit for high-frequency signals.
However, the switching in the transient response clamp circuit 128 depends on only the rising steepness of the waveform of the signal applied to the Vdd line. This may result in a malfunction in the normal operation. The malfunction impairs the reliability of the high-frequency device, and therefore is not allowed. Accordingly, it has been demanded to provide an ESD protection circuit, which can completely eliminate the possibility of malfunction, and thus has high reliability.
An object of the invention is to provide a semiconductor device, which does not malfunction and has high ESD resistance against all the kinds of surges, as well as a method of manufacturing the same.
A semiconductor device according to the invention includes an internal circuit including a semiconductor element, an I/O pad forming a terminal of the internal circuit, a division circuit connected to a lead-in line connecting the internal circuit and the I/O pad, and outputting an electric signal from first and second terminals corresponding to an electric signal applied to the lead-in line and a clamp circuit formed of an MOS transistor arranged between the first and second terminals. The MOS transistor cuts off the conduction between the first terminal side and the second terminal side when a difference in voltage between the electric signal sent from the first terminal side and the electric signal sent from the second terminal side is smaller in absolute value than a threshold voltage of the MOS transistor, occurs the conduction when the absolute value of the voltage difference is equal to or larger than the threshold voltage, and thereby performs the clamping to prevent the voltage applied to the internal circuit from exceeding the predetermined value.
According to this structure, the protection circuit formed of the division circuit and the clamp circuit, which is formed of the MOS transistors, can outwardly pass the surge during a normal operation only when the surge is applied thereto. Therefore, the internal circuit can be protected without receiving any influence. Since the threshold voltage of the MOS transistor can correspond to the clamp voltage, an arbitrary voltage can be set as the clamp voltage depending on the magnitude of the signal voltage during the normal operation as well as a peak voltage of a surge, which is liable to occur, and others. The switching of the clamping function in accordance with the threshold voltage is performed not depending on the steepness of the surge, which is utilized in the prior art, but depending on the voltage value. Therefore, the accuracy is very high, and the high reliability as the protection circuit can be attained. The division circuit may be configured to prevent reverse bias, breakdown and others, whereby the protection circuit can deal with all kinds of surges, and can completely protect the internal circuit. However, in the division circuit described above, the transmission of the surge is not restricted to the transmission in the forward bias direction, and the surge may be transmitted in the reverse bias direction as a result of occurrence of the breakdown.
The clamp circuit described above may be formed of only the MOS transistor provided that the foregoing function can be achieved.
In the semiconductor device of the invention, the MOS transistor may be formed of an n-channel MOS transistor, a drain and a source of the n-channel MOS transistor may be connected to the first and second terminals, respectively, a gate and the drain of the n-channel MOS transistor may be connected together, and a p-conductive well and the source of the n-channel MOS transistor may be connected together. Likewise, the MOS transistor may be formed of a p-channel MOS transistor, a drain and a source of the p-channel MOS transistor may be connected to the first and second terminals, respectively, a gate and the source of the p-channel MOS transistor may be connected together, and an n-conductive well and the drain of the n-channel MOS transistor may be connected together.
By employing the foregoing connection of the nMOS or pMOS transistor forming the clamp circuit, the difference between the voltages applied to the drain and the source can be equal to a difference between the voltages applied to the gate and the channel. As a result, the clamp voltage, which is the potential difference applied between the opposite terminals (drain and source) of the clamp circuit, can be equal to the threshold voltage of the MOS transistor. As a result, the control based on the threshold voltage can be performed to discharge the voltage of the externally applied signal as the surge to the grounded surface without sending it to the internal circuit, or to send the voltage as the signal to the internal circuit.
In the semiconductor device of the invention, it is desired, for example, that the threshold voltage of the n-channel MOS transistor is higher than a voltage applied in a normal operation to an external power supply line connecting the division circuit and an external power supply. It is also desired that the threshold voltage of the p-channel MOS transistor is higher than a voltage applied in a normal operation to an external power supply line connecting the division circuit and an external power supply.
By setting the threshold voltage of the clamp circuit as described above, the voltage equal to or higher than the above threshold voltage can be externally passed as a surge without exerting no influence on the signal in the normal operation. Since the threshold voltage can be arbitrarily adjusted by changing the structure of the MOS transistor, it is very easy to determine a boundary between the signal voltage in the normal operation and the surge voltage.
In the semiconductor device of the invention, for example, the n-channel MOS transistor may have a gate formed of a p-conductive semiconductor. Further, the p-channel MOS transistor may have a gate formed of an n-conductive semiconductor.
According to this structure, a work function is large owing to different conductivities of the gate and the channel so that a high threshold voltage Vth can be achieved easily.
In the semiconductor device of the invention, for example, the division circuit is formed of a p-channel MOS transistor and an n-channel MOS transistor both connected to the lead-in line, the p-channel MOS transistor has a source and a drain, one being connected to the lead-in line and the other being connected to a gate, an n-conductive well and the first terminal, and the n-channel MOS transistor has a source and a drain, one being connected to the lead-in line and the other being connected to a gate, a p-conductive well and the second terminal.
According to the arrangement of the MOS transistors described above, diodes are equivalently arranged, and the division circuit can be formed of only the forward operations of the respective elements in the usual case. Further, the MOS transistor in the division circuit can have a reduced gate width so that the parasitic capacitance can be kept small. Accordingly, the impedance does not become extremely small, e.g., with respect to the high-frequency signal. As a result, such a situation can be avoided that the high-frequency signal is sent to the division circuit at the high priority. However, depending on the waveform of the surge, the position of application of the surge and others, such a case may occur that the surge is not outwardly transmitted only by the forward operations of the MOS transistors forming the division circuit, but is outwardly sent via the reverse operations.
In the semiconductor device of the invention, for example, both the gate widths of the p- and n-channel MOS transistors may be smaller than the gate width of the MOS transistor forming the clamp circuit.
According to this structure, both the two wells of the MOS transistors forming the division circuit can be small, and the capacitances thereof can be small. Therefore, the impedance of the division circuit cannot be extremely small even with respect to the high-frequency signal, and the high-frequency signal, which is lost through the division circuit, can be reduced.
In the semiconductor device of the invention, for example, the division circuit may be formed of two pn junction diodes both connected to the lead-in line and arranged to provide the forward direction directed from the second terminal to the first terminal.
As described above, by arranged the two pn junction diodes, the division circuit can be formed of only the elements performing the forward operations so that the internal circuit can be completely protected from surges in all cases.
In the semiconductor device of the invention, for example, the internal circuit may be a circuit including a silicon MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
In the semiconductor device of the invention, the n-channel MOS transistor forming the clamp circuit may contain a p-conductive impurity in the channel portion at a concentration higher than that of an impurity in the channel portion of the MOS transistor included in the internal circuit. Also, the p-channel MOS transistor forming the clamp circuit may contain an n-conductive impurity in the channel portion at a concentration higher than that of an impurity in the channel portion of the MOS transistor included in the internal circuit.
By increasing the impurity concentration in the channel region, the inversion in the channel of the MOS transistor can be prevented until the gate voltage reaches a high value. Therefore, by adjusting the impurity concentration of the channel region, the threshold voltage can be accurately and easily increased. In the case where the division circuit is formed of the two MOS transistors, the impurity concentration of the channel portion of the MOS transistor in the clamp circuit may be determined based on the MOS transistor in the division circuit instead of the MOS transistor in the internal circuit, and may be higher than the impurity concentration of the channel portion of the MOS transistor in the division circuit.
According to the above structure, inexpensive silicone can be used to provide a semiconductor device having high ESD resistance such as a semiconductor device for high frequencies. The internal circuit described above may be a circuit for high frequencies, or may not be such a circuit.
In the semiconductor device of the invention, the MOS transistor forming the clamp circuit may have a gate insulating film thicker than a gate insulating film of at least one of silicon MOS transistors included in the internal circuit.
According to the above structure, the n-channel MOS transistor or the p-channel MOS transistor in the clamp circuit has the gate insulating film thicker than the gate insulating film of an ordinary MOS transistor, and thereby can have an increased threshold voltage. The on/off control of the channel is performed by the electric field immediately under the gate. As the thickness increases, it is necessary to increase the gate voltage for producing the same electric field. Since the thickness of the gate insulating film can be arbitrarily controlled, the threshold voltage can be arbitrarily set to a high level with good controllability. In the case where the division circuit is formed of the MOS transistor, the thickness of the gate insulating film of the MOS transistor in the clamp circuit may be determined based on the MOS transistor in the division circuit instead of the MOS transistor in the internal circuit, and may be larger than that of the gate insulating film of the MOS transistor in the division circuit.
In the semiconductor device of the invention, for example, the internal circuit may be a circuit for high frequencies.
According to the above structure, the division circuit having a reduced parasitic capacitance can be provided so that the impedance for the high-frequency signal may not be extremely small. Therefore, even if the internal circuit includes, e.g., a silicon semiconductor element, it is possible to provide the semiconductor device having high ESD resistance and good high-frequency characteristics. The internal circuit may include a silicon MOS transistor, or may not include a silicon MOS transistor. The internal circuit may contain or may not contain a semiconductor element of a III-V group compound such as GaAs.
In the semiconductor device of the invention, for example, the division circuit, clamp circuit and internal circuit may be formed on the common silicon substrate.
According to the above structure, it is possible to provide a semiconductor device, which has good surge resistance against all kinds of surges and, e.g., high-frequency characteristics as well as a compact and inexpensive structure.
A method of manufacturing a semiconductor device according to a first aspect of the invention is a method of manufacturing a semiconductor device for a high frequency provided with a protection circuit having a division circuit including MOS transistors of first and second conductivity types, and a clamp circuit formed of an MOS transistor of the first conductivity type. The manufacturing method includes the steps of forming wells of the MOS transistors of the first and second conductivity types of the division circuit as well as a well of the MOS transistor of the first conductivity type forming the clamp circuit in a silicon substrate by implanting impurities of the respective conductivity types; and additionally implanting the impurities of the first conductivity type into a channel portion at a surface portion of the well of the MOS transistor of the first conductivity type in the clamp circuit.
According to the above method, the impurity concentration of a channel region can be higher than a usual value, and thereby a threshold voltage corresponding to a boundary between the signal voltage in a normal operation and a surge can be set to a high value. Since the above impurities can be implanted with high accuracy, the threshold voltage can be set with high accuracy. The well can be formed at the same time as the formation of the well of the MOS transistor of the first conductivity type in the division circuit. Therefore, manufacturing steps can be simple.
A method of manufacturing a semiconductor device according to a second aspect of the invention is a method of manufacturing a semiconductor device for a high frequency provided with a protection circuit having a division circuit including MOS transistors of first and second conductivity types, and a clamp circuit formed of an MOS transistor of the first conductivity type. The manufacturing method includes the steps of implanting impurities of the first conductivity type into a source and a drain of the MOS transistor of the first conductivity type in the clamp circuit and the MOS transistor of the first conductivity type in the division circuit while covering a gate of the MOS transistor of the first conductivity type in the clamp circuit and the MOS transistor of the second conductivity type in the division circuit with a first resist pattern; and implanting impurities of the second conductivity type into the gate of the MOS transistor of the first conductivity type in the clamp circuit and the MOS transistor of the second conductivity type in the division circuit while covering the source and the drain of the MOS transistor of the first conductivity type in the clamp circuit and the MOS transistor of the first conductivity type in the division circuit with a second resist pattern.
By determining the second conductivity type as the conductivity type of the gate of the MOS transistor of the first conductivity type, it is possible to increase the threshold voltage owing to a difference in work function. In this case, the work function is variable depending on the impurity concentration so that the threshold voltage can be changed with high accuracy by controlling the impurity concentration. The step of implanting the impurities of the first conductivity type and the step of implanting the impurities of the second conductivity type may be performed in opposite sequence.
According to the method of manufacturing the semiconductor device of the second aspect of the invention, for example, the arrangement of the first resist pattern may be performed by arranging a simple resist pattern covering only the MOS transistor of the first conductivity type in the division circuit, and the step of implanting the impurities of the first conductivity type may be performed by implanting the impurities of the first conductivity type at a dose smaller than that in the step of implanting the impurities of the second conductivity type using the simple resist pattern.
According to the above structure, it is not necessary to provide the resist covering the gate of the MOS transistor in the clamp circuit. If the gate is provided with a side wall, LDD has a width nearly equal to the maximum thickness of the side wall, and can be smaller than that in the case where the foregoing resist is arranged. This is effective in reducing the parasitic capacitance, reducing the sizes, improving the operation speed and others.
A method of manufacturing a semiconductor device according to a third aspect of the invention is a method of manufacturing a semiconductor device for a high frequency provided with a protection circuit having a division circuit including MOS transistors of first and second conductivity types, and a clamp circuit formed of an MOS transistor of the first conductivity type. The manufacturing method includes the steps of implanting impurities of the second conductivity type while arranging a resist pattern covering the MOS transistor of the first conductivity type on a gate layer covering regions of the MOS transistors of the first and second conductivity types in the division circuit and a region of the MOS transistor of the first conductivity type in the clamp circuit; patterning the gate layer to form gate electrodes of the MOS transistors of the first and second conductivity types in the division circuit and the MOS transistor of the first conductivity type in the clamp circuit; and implanting impurities of the first conductivity type into the source and drain of the MOS transistor of the first conductivity type in the clamp circuit as well as the MOS transistor of the first conductivity type in the division circuit while arranging a resist pattern covering the MOS transistor of the second conductivity type and the gate of the MOS transistor of the first conductivity type in the clamp circuit.
According to the above structure, it is not necessary to form a resist pattern aimed at the gate of the MOS transistor of the clamp circuit, and the resist pattern can have a simple form.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.